The ispClock5312S Evaluation Board is a ready-made platform to help you evaluate and design with the ispClock5300 series of in-system-programmable zero delay universal fan-out buffers. The board includes an ispClock5312S in 48-pin TQFP package and a full set of features to help you use and evaluate the ispClock5312S. All user-programmable features of the ispClock5312S can be easily configured using Lattice Semiconductor's PAC-Designer® software. Learn More

Eval. Board for Lattice ispPAC-POWR1208-01T44I Learn More

Get started integrating multiple power management ICs fast with the ProcessorPM Development Kit. The kit is a versatile, ready to use hardware platform for evaluating and designing with ProcessorPM power management devices. The kit is based on a 2.5” x 2” evaluation board that features the ProcessorPM - POWR605 device in a lead-free 24-pin QFN package, a Power Manager II - POWR6AT6, evaluation circuits that emulate a power supply bus and processor interface, and an expansion header.
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