Lattice delivers the industry’s broadest offering of in-system programmable solutions.

From FPGAs to innovative programmable mixed signal devices, Lattice offers design engineers the means to reduce time-to-market and greatly simplify the system design process.

The LatticeECP3
The LatticeECP3™ FPGA family is the newest addition to the value-based LatticeECP™ (Economy Plus) FPGA series. Utilizing an ultra low power, cost-optimized 65-nm process FPGA architecture, LatticeECP3 extends the functionality of prior generation families to new levels and provides designers with enhanced features and capabilities at a fraction of the power consumption and cost of competing devices.

The LatticeSC
Family of FPGAs combines a high-performance FPGA fabric, 3.8Gbps SERDES and PCS, high-performance I/Os, large embedded RAM, and embedded ASIC blocks in a single industry-leading architecture. This FPGA family is fabricated on a state-of-the-art Fujitsu 90nm technology to provide the highest performance FPGA in the industry.

The LatticeECP2
(EConomy Plus 2nd generation) Family redefines the low-cost FPGA category. Features that the LatticeECP2 family brings to the low-cost FPGA category include high-performance DSP blocks, up to 70K LUT capacity, support for DDR1/2 memory interfaces at 400Mbps and up to 840Mbps generic LVDS performance. The LatticeECP2 also provides enhanced FPGA configuration options with features such as dual boot, bitstream encryption and TransFRTM I/O capability.

The LatticeXP2
devices combine a Look-up Table (LUT4) based FPGA fabric with Flash Non-volatile cells in an architecture referred to as flexiFLASH. The flexi- FLASH approach provides benefits such as instant-on, small footprint, on chip storage with FlashBAK embedded block memories, Serial TAG memory and design security. The parts also support Live Updates with TransFR, 128-bit AES Encryption and Dual-Boot technologies. The LatticeXP2 FPGA fabric utilizes an underlying LatticeECP2 architecture that was optimized from the outset with high performance and low cost in mind. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP blocks.

The LatticeECP2M
Family has the same architecture and basic functions as the LatticeECP2 family but much more embedded memory and high end SERDES features. This makes this family to the first choice if a low cost single chip solution is needed together with fast serial data transfer like PCI Express, Gigabit Ethernet etc.

The LatticeEC & ECP
EConomy Families are designed to offer exceptional functionality, performance and value. Built with an extremely efficient architecture, these low-cost FPGAs deliver sysMEM embedded RAM blocks, distributed memory, sysCLOCK PLLs, DDR memory interface, sysIO buffers, and more. For maximum performance and value, the LatticeECP™ (EConomy Plus) FPGA concept combines the efficient EC-FPGA fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP-DSP (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip.

The LatticeXP
FPGA Family utilizes a combination of non-volatile FLASH cells and SRAM technology to deliver a single-chip solution supporting “instant-on“ and infinite reconfigurability. A non-volatile FLASH cell array distributed within the LatticeXP device stores the device configuration. At power-up the configu‑ ration is transferred from FLASH memory to configuration SRAM in less than 1ms providing an instant-on FPGA. By eliminating the external configuration bitstream and by providing a security scheme that prevents program readback, the LatticeXP Family delivers secure FPGA solutions.
The LatticeXP Family is built on the same proven FPGA fabric as the popular LatticeEC FPGA Family. This highly efficient FPGA fabric is optimized to deliver the best balance of features for cost-sensitive high-volume applications. The LatticeXP Family offers flexible I/O capabilities, distributed

The ispMACH 4000
Family is the industry’s fastest and lowest power ISPTM Complex Programmable Logic Device (CPLD) Family. With a SuperFAST 2.5ns pin-to-pin delay, enhanced logic control, flexible I/O and low dynamic power, the ispMACH 4000 Family is the ultimate solution for high performance systems. The ispMACH400Z Family is a zero power option, pin- and function-compatible with ispMACH 4000V/B/C Devices. Utilizing a low leakage version of Lattice’s advanced E2-CMOS® process technology, the ispMACH 4000Z delivers both, low static power and high speed. Devices operate from a 1.8V power supply resulting in low dynamic power consumption.

The MachXO
Family of non-volatile, infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-capacity FPGAs. The MachXO family combines an optimized Look-Up Table (LUT4) fabric with Lattice’s ispXPTM technology to provide the high pin-to-pin performance and instant-on associated with CPLDs, with the flexibility of FPGAs, all in a low-cost device. The MachXO family offers a high pin-to-logic ratio that is ideal for glue logic, bus bridging, bus interfacing, power-up control and control logic. In addition, MachXO devices feature Lattice’s exclusive sysCLOCKTM PLLs, sysMEMTM embedded memory blocks (EBRs) and high-performance I/Os. These features further facilitate the design of high-speed systems.

ispPAC Power Manager
The Lattice ispPAC-POWR devices incorporate both, in-system programmable logic and in-system programmable analog circuits to perform special functions for power supply sequencing and monitoring. The PAC-POWR devices have the capability to be configured through software to control up to 20 outputs for power supply sequencing and up to 24 comparators monitoring supply voltage limits, up to 6 digital inputs for interfacing to other control circuits or digital logic.

ispPAC Clock Manager
Lattice’s ispClock5600A Family and ispClock5300S Family generate clock nets without using an assortment of zero delay buffers, fanout buffers, termination resistors, delay lines and serpentine clock trace layouts! The ispClock architecture is built around a high performance PLL with programmable input, feedback, and output circuitry. Up to 5 clock frequencies can be generated and routed to any of the output pins. The reference input, feedback input and all outputs can be programmed independently to interface with different I/O standards. Each output’s skew can be individually controlled to compensate for differences in board trace lengths or timing requirements of the receiving devices. In ispClock5600A devices there are 4 configuration profiles stored on-chip for dynamically altering output frequencies for power savings, test modes and other purposes. The ispClock5300S supports implementation of zero delay and non-zero delay fanout buffers in a single device.

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